Desarrollo e implementación de Circuitos Correctores de Errores de baja redundancia para Sistemas Empotrados Distribuidos Reconfigurables

Last 18 September, J. Gracia-Morán presented the paper entitled «Mejora de un Código de Corrección de Errores para tolerar fallos adyacentes bidimensionales» at the Jornadas SARTECO 2019.

El pasado 17 de Septiembre, Juan Carlos Ruiz participó en el panel «Autonomous driving: safety and security issues», celebrado durante el 5th International Workshop on Critical Automotive Applications: Robustness & Safety (CARS 2019), en conlaboración con el EDCC 2019 en Nápoles, Italia.

Last September, 17th, Juan Carlos Ruiz took part in the panel «Autonomous driving: safety and security issues», celebrated in the 5th International Workshop on Critical Automotive Applications: Robustness & Safety (CARS 2019), collocated with EDCC 2019 in Naples, Italy.

Juan Carlos Ruiz ha presentado el artículo publicado «Robustness-aware design space exploration by iteratively augmenting and repairing D-optimal designs», escrito por Ilya Tuzov, David De Andrés and Juan Carlos Ruiz.

Resumen:

Design space exploration (DSE) is nowadays of utmost importance to implement HW designs with acceptable levels of performance, power consumption, area and dependability (PPAD). Electronic Design Automation (EDA) tools support the transformation of HW description models into technology-dependent implementations. Although designers can influence this process by tuning the parameters offered by EDA toolkits, determining their proper configuration is a complex and very time-consuming DSE problem rarely addressed from a PPAD perspective. On one hand, the spatial and temporal complexity of considered targets and the level of abstraction of their descriptions pose problems for the rapid execution of fault injection campaigns. On the other hand, the multi-level nature of parameters offered by EDA toolkits lead to an explosion of possible configurations to exercise during experimentation. This paper shows how to combine the D-optimal design of experiments with FPGA-based and statistical fault injection to significantly reduce not only the number of such configurations but also the number of faults to inject and the time required to perform each injection. All of this without compromising the statistical significance of results. The proposal is exemplified through the Xilinx Vivado Design Suite, which integrates one of the FPGA-based EDA toolkits most widely-used today in the industry, and the MC8051 IP core, a synthesizable microcontroller from Oregano Systems.

Juan Carlos Ruiz has presented the paper entitled «Robustness-aware design space exploration by iteratively augmenting and repairing D-optimal designs», written by Ilya Tuzov, David De Andrés and Juan Carlos Ruiz.

Abstract:

Design space exploration (DSE) is nowadays of utmost importance to implement HW designs with acceptable levels of performance, power consumption, area and dependability (PPAD). Electronic Design Automation (EDA) tools support the transformation of HW description models into technology-dependent implementations. Although designers can influence this process by tuning the parameters offered by EDA toolkits, determining their proper configuration is a complex and very time-consuming DSE problem rarely addressed from a PPAD perspective. On one hand, the spatial and temporal complexity of considered targets and the level of abstraction of their descriptions pose problems for the rapid execution of fault injection campaigns. On the other hand, the multi-level nature of parameters offered by EDA toolkits lead to an explosion of possible configurations to exercise during experimentation. This paper shows how to combine the D-optimal design of experiments with FPGA-based and statistical fault injection to significantly reduce not only the number of such configurations but also the number of faults to inject and the time required to perform each injection. All of this without compromising the statistical significance of results. The proposal is exemplified through the Xilinx Vivado Design Suite, which integrates one of the FPGA-based EDA toolkits most widely-used today in the industry, and the MC8051 IP core, a synthesizable microcontroller from Oregano Systems.

El artículo titulado “Fault Modeling of Graphene Nanoribbon FET Logic Circuits”, escrito por D. Gil-Tomàs, J. Gracia-Morán, L.J. Saiz-Adalid y P.J. Gil-Vicente, y publicado por la revista Electronics, está disponible en el siguiente enlace.

The paper entitled “Fault Modeling of Graphene Nanoribbon FET Logic Circuits”, written by D. Gil-Tomàs, J. Gracia-Morán, L.J. Saiz-Adalid and P.J. Gil-Vicente, and published by Electronics Journal, is now available here.

El artículo titulado “Fault Modeling of Graphene Nanoribbon FET Logic Circuits”, escrito por D. Gil-Tomàs, J. Gracia-Morán, L.J. Saiz-Adalid y P.J. Gil-Vicente ha sido acceptado para su publicación en la Revista Electronics .

Resumen:

Due to the increasing defect rates in highly scaled complementary metal–oxide–semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of growing importance. Understanding and controlling the fault mechanisms associated with new materials and structures for both transistors and interconnection is a key issue in novel nanodevices. The graphene nanoribbon field-effect transistor (GNR FET) has revealed itself as a promising technology to design emerging research logic circuits, because of its outstanding potential speed and power properties. This work presents a study of fault causes, mechanisms, and models at the device level, as well as their impact on logic circuits based on GNR FETs. From a literature review of fault causes and mechanisms, fault propagation was analyzed, and fault models were derived for device and logic circuit levels. This study may be helpful for the prevention of faults in the design process of graphene nanodevices. In addition, it can help in the design and evaluation of defect- and fault-tolerant nanoarchitectures based on graphene circuits. Results are compared with other emerging devices, such as carbon nanotube (CNT) FET and nanowire (NW) FET.

The paper entitled “Fault Modeling of Graphene Nanoribbon FET Logic Circuits”, written by D. Gil-Tomàs, J. Gracia-Morán, L.J. Saiz-Adalid and P.J. Gil-Vicente has been accepted for publication at Electronics Journal.

Abstract:

Due to the increasing defect rates in highly scaled complementary metal–oxide–semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of growing importance. Understanding and controlling the fault mechanisms associated with new materials and structures for both transistors and interconnection is a key issue in novel nanodevices. The graphene nanoribbon field-effect transistor (GNR FET) has revealed itself as a promising technology to design emerging research logic circuits, because of its outstanding potential speed and power properties. This work presents a study of fault causes, mechanisms, and models at the device level, as well as their impact on logic circuits based on GNR FETs. From a literature review of fault causes and mechanisms, fault propagation was analyzed, and fault models were derived for device and logic circuit levels. This study may be helpful for the prevention of faults in the design process of graphene nanodevices. In addition, it can help in the design and evaluation of defect- and fault-tolerant nanoarchitectures based on graphene circuits. Results are compared with other emerging devices, such as carbon nanotube (CNT) FET and nanowire (NW) FET.